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1 features ? operating supply range 3.0v to 3.6v power dissipation 1w max low-power sleep mode (<0.5 mw) rf data channel ? automatic gain control or programmable gain mode ? wide bandwidth vga ? vga accepts inputs from 30 - 300 mv peak-to-peak differential (ppd), 60 - 600 mv ppd or 110 - 1100 mv ppd ? programmable equalization via 7th-order equiripple filter with programmable symmetric zeros ? programmable 5-to-1 filter cutoff range ? data slicer with dc restore circuit ? wide frequency range clock extraction ? frequency synthesizer with independent 7-bit m and 6-bit n dividers, better than 1% resolution ? highly programmable to accommodate dvd (1 - 5x) and cd (6 - 30x) ? write asymmetry measurement for adjusting write mode power ? data recovery supports clv, zclv, zcav recording ? optional internally generated timing for agc and timing recovery servo algebra functions ? 45 mhz bandwidth for differential phase tracking detector ? land and groove detector for dvd ram ? supports one beam push-pull tracking output ? supports one beam differential phase tracking ? focus error signal output ? focus ok signal ? track crossing detection ? mirror signal output ? wobble detection for dvd ram, dvd+rw ? header detection for dvd ram description the at78c1503 is a programmable dvd/cd channel responsible for servo algebra, gain control, equalization, bit detection and clock extraction for cd-rom, dvd-rom, dvd+rw and dvd-ram data. programmable features allow data rates up to 5x dvd. also for dvd-ram functionality, the channel serves the write path providing 1x write clock (wclk) and pit asymmetry detection. the cmos channel operates from a single 3.3v supply and is fully programmable through a serial interface for both cd and dvd modes. dvd/cd read channel at78c1503 rev. 1214c?03/00
at78c1503 2 figure 1. at78c1503 block diagram synthesizer frequency mux focus ok serial register tp1 tp2 rfp/n rg wg pd mode control slow arithmetic and push-pull focus error mirror detector normalization tracking sena sclk sdat mirror rdsz rext 2 trk fe id12 fok te tzc wbl id34 wobble detector land groove detector slowsum sum or difference (idsel) serreg cagc control (rf sequencer) agc control voltage loop cap fcdac/range boostdac rfdrp fo2_cd fo1_cd tr2_cd tr1_cd 2 2 2 2 2 2 rfgen f h g e data5 data4 rclk fref data6 data7 data1 data0 data2 data3 data pll agc control d/se 127 test vref d/se d/se d/se 1 1 1 1 agclz agcfst agchld idsel ap/n bp/n cp/n dp/n pgc pgc pgc pgc mux vga 7th order filter/ equalizer differential tracking detector auto inv track ok track zero cross mux dc restore 8.5x + -
at78c1503 3 figure 2. chip pin out idfield rfp rfn fo1p fo1n fo2p fo2n tr1p tr1n tr2p tr2n fohg rext vdd1 vss1 fo1_cd fo2_cd tr1_cd tr2_cd vdd6 ss_h vss6 reffront refback lenspos trcst vdd3 vss3 vdd11 vss11 data7 data6 data5 data4 data3 data2 data1 data0 rclk rfdrop vdd5 vss5 fref vdd7 vss7 vdd4 vss4 sclk sdata sena atp1 fe te slowsum porb vss8 vdd8 idsel lhipwr shld adcstrt bwup bwdwn idint pd rg vss9 vdd9 wobble id12 id34 tzc tok fok mirror cagc rdsz agclz vdd10 vss10 agcfst agchld tp1p tp1n tp2p tp2n vss2 vdd2 cdcrp cdcrn tsddtp2p tsddtp2n tsddtp1p tsddtp1n trsin1p trsin1n trsin2p trsin2n wg wclk at78c1503 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
at78c1503 4 functional description the at78c1503 is a programmable dvd/cd channel responsible for servo algebra, gain control, equalization, bit detection and clock extraction for cd-rom, dvd-rom, dvd+rw and dvd-ram data. programmable features allow data rates up to 5x dvd. also for dvd-ram func- tionality, the channel serves the write path providing laser power control and pit asymmetry detection. the cmos channel operates from a single 3.3v supply and is fully pro- grammable through a serial interface for both cd and dvd modes. the ic contains two separate processing channels. one for rf signal detection and synchronization, and the other for focus and tracking servo control. these are referred to as the rf channel and the servo channel respectively rf channel overall description the rf channel consists of gain control, equalization, bit detection and clock extraction and is shown in the block diagram of figure 1. the readback signal is internally ac coupled from the preamplifier to the channel input rfp/rfn. a variable gain amplifier (vga) is used for gain control of the readback signal. a 7th order equiripple fil- ter/equalizer is used for noise filtering and equalization of the signal before detection. the output of the equalizer feeds a fixed gain of 8.5 bringing the internal level up to approximately 750 mv peak-to-peak differential (mvppd). the output of the 8.5x amplifier enters the agc control block which closes the agc loop to maintain a 750 mvppd slicer input level while rf p/n is allowed to vary ten to one. the data slicer has a programmable slicing level or an adaptive dc restore system to maintain a dc free output of the slicer. the data slicer output is a digital stream and is sent to the clock extraction and synchronization circuitry. clock extraction is performed with the data pll which is operated in phase/frequency mode during write and idle modes and phase only mode when reading data. an on board frequency synthesizer is used for locking the data pll to a close initial frequency upon start up. various test outputs are provided to aid the evaluation of the system. in addition an offset calibration routine executed on power up eliminates the need for internal ac coupling by correcting internal offsets over the parts operating conditions. gain control the front-end gain control on the at78c1503 consists of five differential variable gain amplifiers (vgas). they include a vga for the rf path and four programmable gain control (pgc) amplifiers for a, b, c and d inputs. the voltage gain range for the vgas can be programmed by setting the vgamode<1:0> control bits (see figure 3). there are two primary modes of operation for the rf path: automatic gain control (agc) mode and programmable gain control (pgc) mode. in agc mode (pgcen=0), the master vga is part of the agc loop. the loop also contains the 7th order filter/equalizer, a fixed high-gain stage, an amplitude detector, a dual rate charge-pump, an internal loop filter/capacitor and an exponentiator (see figure 3). the vga voltage gain is adjusted by the feedback control loop such that the signal at the input of the amplitude detector is about 750 mvppd. gain tracking is achieved by applying the same gain control signals to the four slave vgas. figure 3. agc loop block diagram in pgc mode (pgcen=1), the master vga gain is set directly by programming the pgc dac through the serial interface (see table 5). once again, gain control signals are shared between the master and the four slave vgas. the agc loop is of the peak sampling type in which asymmetric charge/discharge currents are used. these currents are programmable through bits agcqp<3:0> (see table 4). they are derived from the internal bandgap voltage reference and the external resistor rext, resulting in a near zero temperature coefficient. the absolute value is process dependent varying with the internal bandgap voltage (5%) as well as due to tolerance of the external resistor. the charge current continuously charges up the agc capacitor. a 16x discharge current results for the duration the signal is above the 100% threshold (i.e. 750 mvppd). the large discharge/charge ratio causes the loop to adjust the vga gain based on the peak amplitude of the signal. as a result, the peaks of the signal are locked to a known voltage (i.e. 750 mvppd). rf in vga filter equalizer 8.5x qpump amplitude detector exp cagc 350pf to detector internal
at78c1503 5 figure 4. rf agc timing sequence using the on-chip sequencer agc mode is initiated when either read gate (rg) or idfield transition high. initially, the input impedance is reduced (lowz=1) and the agc loop is set in hold mode so that no gain corrections are made. an external agchld pin is also provided for the user to initiate agc loop hold whenever desired. after a user programmable duration, controlled by bits agclztm<3:0>, the lowz signal goes low. conversely, it is also possible to set the lowz signal low, through the external agclz pin. following lowz, a user programmable period is set aside to allow the internal ac-coupling networks to recover. this duration is controlled by programming bits accpltm<5:0>. next, the agc goes into a fast acquisition mode. during fast acquisition mode, the charge pump current, and consequently the agc loop bandwidth, is scaled up by a factor of 4 as compared to normal operation. the loop capacitor is quickly charged/discharged until the lock voltage is 750 mvppd. this period is set by either the external agcfst pin (high) or by programming bits agcfsttm<5:0>. after fast mode, normal agc operation starts and continues until rg goes low. figure 4 illustrates a typical timing sequence for the agc loop using the on-chip rf sequencer. for a more comprehensive description of user programmable timing, please refer to the section on the rf sequencer. the rf signal, whether in agc or pgc mode, is generated in a few different ways. if rfgen is low, an externally gen- erated differential rf signal is ac-coupled to the master vga at pins rfp/n. at the same time, a, b, c and d differ- ential signals are also ac-coupled to each of the four slave vgas at pins ap/n, bp/n, cp/n and dp/n respectively. for single-ended input, all signals are ac-coupled to the respective positive pin while the negative pin is connected to a small-signal ground. it is also possible to generate the rf signal internally by summing the four individual signals a, b, c and d. this is achieved by setting the control bit rfgen high. the rf signal in this case is a+b+c+d. however, if the idsel con- trol signal is also asserted while rfgen is high, then the rf signal is generated as a difference instead of a sum. this happens during headers or id fields on a dvd ram. the rf signal in this case is a+b-(c+d). the idsel signal has no effect on the rf path if rfgen is low. under these circumstances, it is assumed that the preamp is capable of generating the difference. for a complete description of various modes and the respective rf signals, please see table 19. the agc loop has one test point, which can be monitored by the user. the test point designated as tp1 is dedicated to the agc circuitry. tp1 allows the user to monitor the inputs and outputs of all five vgas, the signals out of the three summer/buffers and the input/output of the high gain amplifier. the test point has a selection bit tp1en, and address bits tp1<5:0>, which are selected via the serial register. the test point map for tp1 is given in table 6. the test point gains are lower than unity. this means that test point output signals are scaled-down versions of the internal signals being monitored. tp1 has a gain of 0.8 v/v from the internal nodes. this gain must be used in calculating certain absolute voltages stated in the spec, for example, the agc lock voltage of 750 mvppd. an additional serial register bit, agccaltpon, is provided to configure the test point as if the calibration routine is being used. the address mapping changes according to table 7. calibration is an internal offset cancellation scheme used at various points throughout the channel. during calibration, the unbuffered output node of each of the five vgas is offset corrected. the fixed, high-gain amplifier is also calibrated in a similar fashion. for more information on calibration, please refer to the calibration section. rf dropout detector the rf dropout detector is used to sense when the rf signal has dropped below a programmable level for a rg or idfield lowz/hold 1-15 clocks (agclzztm<3:0>) ac coupling recovery 1-63 clocks (accpltm<5:0>) 1-63 clocks (agcfsttm<5:0>) agc fast
at78c1503 6 specified amount of time. the rf dropout detector gets its input from the 8.5 v/v gain stage immediately before the dc restore block. there is a programmable window detector which the rf signal passes through. the absolute value of this window has the following value: (rfdth<4:0>+1)*3.5 mv+115 mv. the result of this comparison is captured by comparators clocked at the synthesizer clock rate divided by two. the output of the window comparator enters a counter in which the duration of the assertion of the window detector is monitored. if the window detector output remains asserted, longer than rfdropcnt<4:0> system clocks, the rfdrop pin will be asserted. the assertion of the window detector indicates the rf signal is below the programmed value. the rf dropout detector clock is the synthesizer rate divided by two. once the signal has been restored in amplitude, the rfdrop pin will be deasserted. there is no attempt to make use of this signal internal to the channel. in order for the rf dropout to operate the rfdropen bit must be programmed high. when this bit is low, the dropout detector will be powered down. 7th-order filter/equalizer the on board filter/equalizer is implemented as a 7 pole 2 symmetric zero 0.05 degree equiripple phase low-pass filter. cutoff frequency for the filter spans 4 - 26 mhz in 6 coarse steps, set by serial register 9, fltrrange<2:0>, with fine control within each coarse step controlled by a 6- bit dac; fcdac<4:0>. two programmable zeros provide user controlled boost up to 14db from the low frequency gain. the two zeros may be set to track one another, asymbst=0, to provide flat group delay independent of boost or the zeros can be programmed independently thereby providing group delay adjustment, asymbst=1. in the case of symmetric boost, bst1<3:0> controls the amount of boost; see table 30. for asymmetric zeros, bst1<3:0> and bst2<3:0> independently control the two zeros. group delay variation is maintained within 4% out to 1.5 times the cutoff frequency when asymbst=0. individual q adjust is also provided for the three biquads which make up the filter. these qs can be independently adjusted if a slightly different transfer function other than the equiripple is desired. the amount of q adjust is determined by serial registers bqd1-3q<3:0>, see table 31. when boost greater than 7 db above the dc level is required, the gain through the filter needs to be reduced in order to reduce the amount of signal distortion originating from the filter. the bit fltrgain should, therefore, be set high when more than 7db of gain is required, this will reduce the signal amplitude through the filter by a factor of two. the filter cutoff is stabilized over supply and temperature variations by using an external resistor and an internal con- trol loop. absolute cutoff is guaranteed within 10% of the specified value. the filter is incorporated into the agc loop along with a final gain of 8.5 v/v amplifier to bring the final detector input up to 750 mvppd. the signals at every point throughout the continuous time filter (ctf) are available via tp2 for testing and system evaluation, see table 8. rf data detector and dc restore the output of the high gain amplifier inside the agc loop is the input to the rf detector. the detector can be operated in three distinct modes controlled by bits detmode<1:0> (see table 10). these modes are dc-restore mode, com- parator mode and write power test mode. during normal operation (dc-restore mode), the detector is a slicer with the slicing threshold set automatically by an internal feed back loop. this is depicted in figure 4. figure 5. data slicer with dc restore the loop consists of a charge pump and an external inte- grating capacitor. the digital output of the slicer is integrated and subtracted from the input removing any baseline variation. the charge pump current is programma- ble and can be set through bits detcpi<1:0> and detkcp<1:0> in the serial register. in comparator mode, the feedback loop is disabled and the slicing threshold is set manually by programming a detthrsh. lastly, in write power test mode, the detector is used in asymmetry detection for determining written pit asymmetry. in this mode the feedback loop is disabled, the loop filter/capacitor is reset to zero and the digital output of the slicer is inte- grated. the resulting voltage is then used to adjust the write power to be within some desirable range. a number of detector internal signals can be monitored at test point tsdd1<3:0> (see table 14). these include, the voltage on the loop filter/capacitor, the input to the slicer input, and the digital output of the slicer. slicer detector output vth 0 vth dac c qpump eq data - + 2 2 2
at78c1503 7 timing recovery pll the digital data out of the rf data detector is input to the data pll. the purpose of the data pll is to extract the system clock from the detected data and synchronize the clock and detected data. the data pll consists of phase/frequency comparator, phase only comparator, 2 to 1 multiplexer, charge pump, internal loop filter and vco. two outputs are generated. one is the retimed data available to the controller on a 4 or 8-bit bus and two is the recovered clock with frequency equal to the recovered channel data rate divided by 4 or 8, depending on the nibble bit state. prior to the start of a read operation, the data pll vco is locked to the frequency synthesizer output which is programmed to the desired channel rate. this sets the data pll vco close to the desired frequency for read back. locking the two plls is accomplished by choosing the frequency synthesizer output and the data pll vco as the inputs to the data pll phase/frequency detector (pfd). the timing recovery system operates in two modes of operation. when the syncsrch bit is programmed high the data recovery vco clock is initially slaved to the synthesizer output. a maxperiod counter is updated at each data transition. the period counter counts the number of clock cycles between transitions and resets at each transition. the maxperiod register holds the maximum of its present value or the period counter value at a transition. if the vco is at the proper frequency, the maxperiod counter value will be 14 in dvd rom, dvd ram and dvd+rw modes of operation. this corresponds to the 14t sync frames in the data. if the maxperiod counter value is not 14, the data recovery ico current dac, drdac, will be adjusted to set the vco frequency so the longest time between transitions is 14 clock cycles. the maxperiod counter is validated over a period tbd clock cycles. after the maxperiod counter has maintained 14 as the maximum for tbd clock cycles the drdac is set to within 7% of the proper frequency. the number of clock cycles between 14t patterns is counted by an 11-bit counter. when the drdac is set to the proper current, the time between 14t patterns is 1456 clock cycles. this signifies the timing recovery vco is operating at the correct frequency and the data recovery pll will pull in. the drdac is incrementally adjusted to realize the time between 14t patterns being 1456 clock cycles. the controller is able to read the drdac setting and the maxperiod counter via the serial register to assist setup of the equalizer and detector. when the 78c1503 is operated in cd mode the ico dac is adjusted to cause the maxperiod counter value to equal 11 clock cycles between transitions. again, the max- period counter value may be read by the serial register. if the syncsrch bit is programmed low all control of the synthesizer and vco is done by the controller. when rg is asserted the detector output is used instead of the frequency synthesizer output for the phase comparison. in this mode the phase only comparator is used. the loop filter is implemented with on-chip components, the transient characteristics of the loop are set internally based on the dvd readback rate. the loop filter components and charge pump currents are programmed using the serial register. the loop filter component values and currents are chosen such that the loop filter damping factor equals 1.2. the loop filter crossover frequency is nominally set to 1% of the data rate during acquisition and 0.5% of the data rate during track. the loop filter charge pump current values and loop filter component values are listed in table 17. a block dia- gram of the data pll is shown in figure 6. figure 6. timing recovery phase locked loop frequency synthesizer pll the frequency synthesizer generates a frequency reference for the timing recovery pll in all write and idle modes and also generates a frequency reference for writing data in a dvd/ram application. a block diagram of the synthesizer is shown in figure 7. the frequency synthesizer consists of phase/frequency comparator, charge pump, internal loop filter, vco and internal dividers for generating all frequencies needed for dvd and cd operation. the frequency can be programmed with an accuracy better than 1%. the internal loop filter is fully differential to suppress common mode noise. pfd synthesizer output qp vco pd detector output write/idle read recovered data cp cs r
at78c1503 8 figure 7. synthesizer phase locked loop an external cmos level clock reference (fref) divided by a programmable 7-bit counter (m) and is used as a stable reference input to the phase frequency detector. the second input to the phase detector is the vco divided by n+1, where n is an 6-bit programmable counter value. the clock output comes from the vco divided by p+1, although this 3-bit counter can divide by one. frequencies from 25 mhz to 150 mhz are supported with better than 1% resolution. the external frequency reference, fref can also be divided by two before it is sent into the m counter set by frefby2 bit. the clock frequency output to the data recovery section of the at78c1503 is: f clock =[(f ref or f ref /2)(n+1)]/[(m+1)(p+1)] tr and synthesizer loop parameters the product of the two above parameters gives: tr and synthesizer loop equations where: n = loop ? s natural frequency (rad/s) = damping factor in = charge pump current divided by average number of bit times per vco update (a). for reading random data, divide charge pump current by four to get in. cs = series capacitor in loop filter (f) r = resistor in loop filter (w) kvco = vco gain (rad/sv) cp = cs/20 (f) figure 8. photo diode array v-to-i g m = 98 ma/v (higm = 1), 70 ma/v (higm = 0) k ico = 50% of f c /100 ma g m k ico = k vco = 49% of f c /v (higm = 1), 35% of f c /v (higm = 0) pfd qp vco 1/(n+1) clock 1/(m+1) fref or cp cs r 1/(p+1) fref/2 n in kvco ? () 2 () ? cs -------------------------------------------- = r2 ? () in cs kvco ?? () 2 () ? ? = a d b c f g e h track direction
at78c1503 9 figure 9. fast servo arithmetic servo channel description the at78c1503 servo channel can process data from two types of photodiode arrays. the most common type is the a,b,c,d only array. the other type of array is an 8 element array (see figure 8) in which differential push pull tracking or push pull tracking may be used. as shown in figure 1, there are 4 differential signals: ap/n, bp/n, cp/n, dp/n. these inputs can also be used in a single ended fashion by not connecting the negative side and also setting bit tbd in the serial register to indicate that a single ended interface has been selected. in addition to the differential a, b, c and d input signals the outputs of the e, f, g and h photo diodes are connected as single ended input signals to the 78c1503 to be used in the differential push-pull tracking algebra. servo algebra is performed for focus, push-pull tracking, differential phase tracking, tangential push pull and land/groove detection. the input signals on the a, b, c and d pins are used to internally generate the astigmatic focus and tracking error signals. additionally the input pins e, f, g and h may be used to internally generate the differential push-pull tracking signal. a block diagram of the fast servo arithmetic functions are shown in figure 9 and a block diagram of the slow servo arithmetic functions are shown in figure 11. fast servo arithmetic functions differential phase tracking the differential phase tracking block diagram shown in figure 9 generates the servo tracking error for dvd rom. differential inputs a, b, c and d, are ac-coupled using on- chip capacitors. the ac-coupling pole is nominally set to 6 khz. each of these differential signals then goes through a programmable gain control (pgc) set up via the serial register. the pgcs are followed by adjustable delays nominally set to tbd ns. the delays on the signals from the front of the detector, a and d, are adjusted to an amount that is greater than the nominal delay, whereas the delays on signals from b and c signals are adjusted to , = less than the nominal delay. the delayed signals are followed by two high-speed summers to generate the diagonal sums a+c & b+d. the output signals of the summers is delayed by a different nominal value plus and minus an adjustable amount, . = that is, the output a+c is delayed by a nominal amount plus an adjustable amount, , = and the output b+d is delayed by the same nominal value minus . the adjustable delays are realized with second-order all pass bessel filters. the signal level coming out of the second set of delays is typically between 100-150 mvppd. each of the two diagonal sums is buffered, amplified and equalized. the equalizer transfer function is depicted in figure 10 and includes a zero followed by two poles. the zero and the two poles track the dvd setting according to table 20. equalized diagonal sums (a+c & b+d) are sliced around a fixed threshold and phase compared to generate pump-up and pump-down pulses. the phase comparator output is automatically disabled when no transitions are detected on either one of its two inputs. following the phase comparator is a low-pass filter which integrates the pump-up and pump-down pulses to generate the differential phase tracking error signal. the low-pass filter consists of a charge-pump and on-chip integrating capacitors. the pole frequency is programmable from 30 khz to about 2.5 mhz. when dpddivsel is high, the pole frequency can be set directly through bits dpddivhi<3:0> (see table 23). when dpddivsel is low, however, the low-pass cutoff frequency is adjusted automatically by an up/down counter. this feature allows the low-pass filter bandwidth to track seek speeds during seek mode. a user- 2 2 2 2 b+d a+c lpf 2 2 lpf qp cp/n dp/n ap/n bp/n vga vga vga vga vga vga eq eq pd te 2 2 dpdkpgc<3:0> 4 dpdvgabyp dpdlpfbyp from serial register differential to single-ended converter plus vga up dn dpdksevga<3:0> 4 del del del del del1 del1
at78c1503 10 programmable dac allows up to 250 mv of offset correction at the charge-pump output to compensate for any mismatches in the two signal paths. the low-pass filter output is fed into a differential-to-single- ended converter followed by another vga. this vga has a gain range from 0.5v/v up to 4v/v controlled by bits dpdksevga<3:0> (see table 21). the final output is centered around 1.5v with a range of about 500 mv. this output is muxed-in with the te (tracking error) signal for dvd ram. figure 10. differential phase tracking eq transfer function 20 db/decade -20 db/decade 20 db/decade 1 2 3 4 5 mhz 3.4 mhz 17 mhz 40 mhz 0 db
at78c1503 11 slow servo arithmetic functions figure 11 shows the top level diagram for the slow servo. the first block has inputs a, b, c, d,e, f, g and h. the functionality is as follows: first there is a sample and hold function on all the 4 inputs. the s/h is done from an external cmos input pin tbd. the minimum amount of time for the hold state is 30 ns, and it should not exceed 200 ns. the minimum amount of time for the sample state depends on how much the sig- nal changes between samples. for example if ak+1 - ak is half of the dynamic range on fo1,2 tr1,2, then the sample state should not be less than 20 ns. in reality the s/h signal will be slew rate limited by the cmos i/o input. second there is a differential to single ended conversion and a vga function on each input. the reference for the d2s function is referenced from the supply and it varies from vdd-1.5v to vdd-2v via a 3-bit d/a. this reference is also sent as an output off chip, in case it needs to be used to a reference in a preamp. the vga range is between 0.3 to 4 (16 exponentially spaced steps) with a worst case bandwidth of 15 mhz. the vga outputs go also to id detector, wobble detector, and mirror field detector blocks. there is also an option which resets the values of a, b, c and d to their midrange point (ex. 0v differential). this option is used for electronic offset correction on the focus error and tracking error signal described later in this section. for the slow servo each of the four inputs contains a single pole low-pass filter with a programmable cutoff frequency between 150-500 khz. the cutoff frequency is programmable with a 3-bit sr control which does not track the channel data rate. next block is a voltage to current converter followed by a 30% gain adjust (4 bits + sign) and a 30% offset adjust (4 bits + sign) on each individual channel. the input signals a,b,c,d will get the gain and offset adjustment. these gain and offset adjusted signals are now summed together and the sum feeds a digitally controlled agc loop (also known as the normalization loop). maintaining a con- stant output voltage at the output of the agc loop normalizes the input to the focus and push-pull tracking error signals, so the error signals are not dependent on the strength of the light returned to the photo-diodes. this nor- malization alleviates differences due to media reflectivity. this loop consists of a vga, counter (7 bits) and compara- tors. the clock for the counter is selectable: it can either be a divide by 3*x of the data rate (x ranges between 3 and 16) or a divide by 3*y of the oscillator frequency (y ranges between 1 and 16). the reason behind the two different clock domains is that when the normalization loop is used for normal operation (read, erase, write) collecting data along the tracks, will be desirable for the loop bandwidth to follow the data rate. for the tracking error during a seek however, it might be desirable for the loop bandwidth to be independent of data rate. the normalization loop has a fast acquisition mode controlled by 2 bits tbd. depending on this setting the counter can count by either 1,2,4,8 every time when the error signal exceeds a threshold which is also programmable by 2 bits tbd. this feature helps the normalization loop track fast slewing signals in the a+b+c+d signal. focus error signal (fe) fe = (a+c)-(b+d). the fe signal is then passed through a vga which is slaved to the normal- ization loop. the dynamic range on the fe is between 0.5 to 2.5v centered around 1.5v. there is also a +-0.5v offset added to the fe signal using a 3-bit + sign d/a. in addition, the gain on the focus error is adjustable between 1 to 5 using a 3-bit gain adjust (exponentially spaced). there is high gain chip input tbd which flips between gain = 1 and the gain set by the 3-bit gain adjust. for the gain of 1 set- ting the fe is linear and covers 0.5 - 2.5 range. for a gain higher than 1 the fe will saturate. push pull tracking error signal (pptk) is pptk = (a+b)- (c+d). the pptk signal is then passed through a vga which is slaved to the normalization loop. the dynamic range on the pptk is between 0.5 to 2.5v centered around 1.5v. there is also a 0.5v offset added to the pptk sig- nal using a 3-bit + sign d/a. in addition, the gain on the tracking error is adjustable between 1 to 5 using a 3-bit gain adjust (exponentially spaced). for the gain of 1 setting the pptk is linear and covers 0.5-2.5 range. for a gain higher than 1, the pptk will saturate. the differential push pull tracking error is dpptk=(a+b+e+f) - (c+d+g+h). the differential push pull tracking error signal is passed through a vga slaved to the normalization loop and conditioned similarly to the pptk error signal as described above. the track zero crossing (tzc) signal is needed for counting tracks during a seek operation. part of the tzc function is an average detector function (see figure 11) which follows the average of either the pptk or dfte (differential phase tracking error) signals. the architecture of the average detect function (adf) is similar to the normalization loop. the only difference is that rather than keeping a constant output, this loop follows the input with different bandwidths. the clock frequency for this adf block is a divide by 2*x of the crystal, where x is between 1 and 2048. the maximum clock frequency however should not exceed 8 mhz. this bandwidth is controlled by 2 input pins (bwup, bwdwn). when each of these pins is toggled by the servo chip the bandwidth of the adf macro goes up or down by a factor of 2. there are 11 steps for the bandwidth.
at78c1503 12 figure 11. slow servo arithmetic this big bandwidth range is helpful because it can track in real time, the head velocity during a seek. when bwup and bwdwn are both high, the loop bandwidth point to a location in the serial register. the comparator which compares the output of the adf block with the incoming signal (pptk or dfte) has a programmable hysteresis with a maximum value between 50 to 300 mv. for a given setting the hysteresis goes down at 6db/octave (4 points) as soon as tzc bandwidth equals the bandwidth at the front end of the servo block (200k to 500k). the total range that the hysteresis varies is 4 to 1. this is done in order to reduce the hysteresis of the comparator as signals faster than the servo lpf setting (200k-500k) are passed through the system. for example assume the front end lp is set at 200k and the comparator hysteresis is set at 100 mv. then, as the bandwidth of the tzc goes higher than 200k the hysteresis is as shown table 19. the mirror circuit for dvd rom has the same function as the track zero crossing. the only difference is that its input is the total sum a+b+c+d. this circuit shares the same bwup, bwdwn inputs as the tzc circuit and also shares the same register location for the default bandwidth. the hysteresis, however, for its output comparator is a different register location (50 - 300 mv). the total sum a+b+c+d is sent off chip to the servo controller. the dynamic range is 0.5 to 2.5 volts. on the same output pin, we also mux a, b, c and d, in order to perform the 30% gain and offset adjust discussed earlier. the bandwidth of the total sum output is 100 khz. there is also the refback reference pin, (typically 1.5v from ground), which when configured as an output, reflects the reference of the signals going to the servo adc. when the reference is configured as an input, (with a sr bit tbd) then the external reference is used to output the signals to the servo adc. the mirror field detector is different from the mirror for dvd rom. this circuit monitors the total sum before the 200- 500k lp and using a programmable threshold comparator controlled by bits tdb in the sr flags the mirror field. the focus ok and track ok signals output a cmos logic high signal during write when the focus error signal or tracking error signal is too large. the signals are derived from the write gate input signal being true and their respective error signals being greater than a preset value. this is schematically drawn in figure 12 for the focus ok signal. figure 12. focus nok id header detection the id header detection circuit determines when a header has occurred in the case of dvd ram media. after gain adjustment, ac coupling and lowpass filtering the difference channel, left minus right halves of photo detector array, will produce a dc shifted signal indicating the presence of the dvd ram header. the standard dvd ram format also includes a second header, immediately vga comparator/ dac a + b + c + d fe pptk counter landgrvdet id12 level dac -1 id34 > < (a + b)-(c + d) bpf wbl wbl thrsh > slowsum mirror dvd rom > variable thresh mirror field mux 4 fo1,2 tr1,2 average detector > hysteresis comparator threshold tzc average detector > hysteresis comparator threshold mux pptk dfte offset offset fo1_cd fo2_cd tr1_cd tr2_cd vga vga s/h/d2s vga/lpf/ v21/gain & offset adjust a b c d e f g h > & write vfcsnok fcs fok < vfcsok & inv +
at78c1503 13 proceeding the first, with opposite polarity which the detector will also sense. once a header occurs, the assertion and deassertion of the id12 and id34 pins will coincide with the detection of the first header and second header, respectively. the polarity of the tracking error (te pin) will also be adjusted to correspond to the proper land/groove polarity which is determined by the sign of the dc shift of the first header. the beginning of a header also can start a new rf sequence, which will provide the rf data recovery path with the correctly timed control signals. the rf sequencer is explained in the next section. the difference signal used by the id detector is generated automatically from the input signals. the difference signal is the sum ap/n+bp/n-(cp/n+dp/n). the difference signal passes through a fixed gain of 3 v/v before passing through a programmable gain stage with transfer function equal to idwblvga*0.25 v/v. this difference signal is internally ac coupled with a pole at 2 khz. the signal then goes to a 2nd order lowpass filter which has a dc gain of 2 v/v. the cutoff frequency of the lowpass filter is set by the idwblfltr<2:0> bits and has a value of (idwblfltr+1)*100 khz which allows for dvd ram x1 through x8 headers to be detected. after filtering, the signal goes to a window comparator which is clocked at a synthesizer divided by 8 rate. the absolute value of the window threshold is set by the idslc<3:0> bits and has a value of idslce*26.2 mv. when the signal exceeds the programmed window, it triggers the id detector state machine. the analog signal polarity for id12 determines if the push- pull tracking error is negated or not, i.e. indicating the start of a land or a groove. if the polarity is positive, then a groove region is being entered and the polarity of the tracking error is not negated. if the polarity of the signal is negative, then a land region is being entered and the sign of the tracking error is negated. the polpol bit (polarity of the polarity), allows an inversion of the above stated logic in the case that an inversion has occurred along the signal path. the snglhdr bit is provided if the media being read has only a single header. this allows the id detector state machine to be reset following only one header. the idint serial register bit gets logically or ? ed with the idint pin which enables the internal id detector to trigger the rf sequencer. if neither one of these signals are asserted, the rf sequencer will not be triggered by the detected header but the id12/id34 pins are still active as is the polarity switching of the ram tracking error. the idhld bit allows the part to disable the id detector from functioning except when the idsel pin is asserted. this in effect forces the part to qualify a valid header with the idsel pin. this is helpful once header timing is acquired and the controller can assert idsel at approximately the correct time when a header is about to occur as this prevents possible false triggering of the id detector during user data periods. the idfldsrce bit controls what signal will become the output on the idfield pin. when idfldsrce is low, the idfield pin tracks the idsel input directly. when idfldsrce is high, the idfield output will brought high upon the assertion of id12 and return low upon the deassertion of id34. in the case of snglhdr being high, idfield will be brought low upon the deassertion of id12.this allows the channel to generate its own idfield signal upon start-up of the system if this signal should be required by the preamp before the controller knows the exact timing of the ram headers. all id detector functionality will be disabled if the mode con- trol bits, srvmod<3:0>, are such that ram media is not selected. for test purposes the by_acbyp bit is provided which shorts the signal path around the ac coupling capacitor. this allows dc testing of the id and wobble paths. hdrtsten allows the id detector state machine to be tested. when asserted, the agclz pin functions as the positive window comparator output, agcfst functions as the negative window comparator output and agchld functions as the wobble comparator output. using these pins the detector and rf sequencer can be tested by a purely digital means. rf sequencer the rf sequencer provides the capability to internally control the rf paths timing sequence when entering a header area for ram or user data for any supported media. the rf signals which it controls are the agcs ? lowz, hold and fast recovery signals and also the signal to indicate the need to switch to data mode in the timing recovery block. when enabled, the sequencers outputs are logically or ? ed with the corresponding external pins and is especially useful at start-up when the controller doesn ? t know the exact laser position yet. the sequencer may be started in several ways, all of which may be enabled or disabled. in dvd ram header mode, the sequencer may be started with the assertion of the internally generated id12 and id34 or the external input pin idsel. the choice of which mode the sequencer starts with is determined by the state of the id internal (idint) pin. if idint is asserted, logically high, the internally gener- ated id12 signal is used to start the sequencer. this is useful under the condition that the controller does not yet know the laser location, or the controller does not contain the circuitry required to generate the control signals, or the user believes the channel can more accurately detect the
at78c1503 14 headers than the controller can time them. if idint is not asserted, it is set logically low, then the external pin idsel may be used to start the rf sequencer. this mode is use- ful if the controller does not contain the required logic to generate the rf signals or if fewer inter-connects between the controller and channel were desired. in all types of media, the rf sequencer may also be started with the assertion of the pin rg. the rf sequencers system clock is derived from the fre- quency synthesizer divided by four so it is therefore clocked at a nibble rate with respect to the rf channel rate. as stated above, the start signal for the sequencer can be one of several possibilities. the lengths of each timing field are user programmable and are all stated in terms of nibble rate. figure 1 shows the generated signals and the amount of programmability for each field. lowz/hold line is shown starting asserted. this would be the typical case when entering a ram header or a user data field. as stated above, the start signal can be either the rg pin or one of several id header indicators. in the case of ram headers, the lowz needs to be asserted in order for the on-chip ac coupling to reject the large dc shift present in the header. once the dc shift has passed, the ac coupling pole is internally reduced at a controlled rate in order for no dc offset to be stored on the ac coupling capacitors. the amount of time to allow the ac coupling pole to be brought down is controlled by the accpltm bits. once the pole has been reduced an agc fast attack mode is entered. the details of this mode are explained in the agc section. the amount of time to remain in this state is controlled by the agcfsttm bits. after the agcfsttm has timed out, the dc restore block and timing recovery pll are allowed to begin reading user data. the rsttm allows the sequencer to deassert the id12/id34 lines. this is useful when the exact length of headers are known so that the analog id detector does not need to accurately detect the end of the ram headers. there are several other control bits for the sequencer which will now be described. for standard dvd ram media there are two dc shifted headers immediately fol- lowing one another. for non-standard ram media, where only a single header is present, the snglhdr bit should be programmed high. this allows the sequencer to only time-out a single header, rather than the assumed two headers. this feature is used when the hdratmg, (header auto-timing bit), is asserted. when the auto timing feature is enabled, only the leading edge of the header, i.e. id12, needs to be accurately detected by the id detector. since the user knows the exact length of the headers on the media, the rsttm can be programmed to accurately put the rf path in lowz mode when the header is com- pleted. this is useful since the analog detector may be susceptible to noise and ma,y therefore, not time-out at the exact time. when in double header mode, snglhdr=0, the sequencer will automatically generate the second rf sequence when headers 3/4 are present independent of id34 signal. the ramread bit allows an internal signal which controls the source for the timing recovery to be controlled by the sequencer to properly set the reference for the timing recovery when reading ram media. this bit needs to be programmed low when a ram data read operation is first started and then may be programmed high while reading ram data. when ramread is high, the timing recovery pll will automatically go into a phase/frequency mode when entering a header. this allows very fast frequency acquisition onto the preamble present at the beginning of ram headers. the sequencer will also automatically put the timing recovery into a coast mode between headers and also in the gap fields present at the beginning and end of the headers, before and after user data. the sequencer can also produce the required timing sequence off the leading edge of rg when rgstrt, rg start, bit is low. when this bit is high, no sequence will be generated from the leading edge of rg and it is assumed that the controller is providing the proper agc timing signals. the datrefst, (data reference start bit), allows the internal signal, which controls the reference, either the synthesizer or data, for the timing recovery to come directly from the idfield or rg pins when datrefst is high. this will effectively bypass all sequencer signals which control the timing recovery block. a dissqcr bit is also provided to disable the entire sequencer when it is programmed high. when not in ram mode, internal logic will also prevent the sequencer from starting on any other signal other than rg.
at78c1503 15 figure 13. rf path timing sequence wobble signal detect the wobble signal passes through the same signal path as the id header signal up through the ac coupling. the wobble signal is extracted with a bandpass filter, 2 zeros and three poles. while operating with dvd ram media the filter passband is centered at (idwblfltr+1)*157 khz with 20 db of passband gain. the center of the bandpass filter for dvd+rw media the passband is centered at (idwblfltr+1)*817.5 khz. the output of the fifth order bandpass filter is the input to the wobble pll block. a block diagram is shown in figure 1. the output of the bandpass filter is the input to the wobble clock generation block and to a threshold comparator which is compared to the wbllvl<1:0> setting. the output of the comparator is clocked with the 2x wobble clock, which is derived from the wobble signal squared. if the output of the bandpass filter is larger than the programmed level the output of the wobble data flip-flop will be high. the input of the flip-flop and output are input to an xor gate to determine the phase transitions in the adip signal. the comparator trip point is determined by a combination of the wbl en bit and wbl<1:0>. if wbl en is low, then the comparators reference level is set to zero and the wobble signal appears ideally with a 50/50 duty cycle, during the monotone wobble signal, and will detect the. if wbl en is high, then the comparator ? s trip point is shifted from zero to the value shown in table 33. the blkwbl bit allows the wobble pin to be held low while reading through a dvd ram header. the hdrtsten, header test enable bit, allows the wobble path logic to be tested. when it is programmed high, the agchld pin will appear at the wobble pin output. the wobble signal will be disabled if not in a dvd ram mode, see table 27. figure 14. wobble pll block diagram start signal lowz/hold 1-15 clocks (agclztm<3:0>) ac coupling recovery 1-63 clocks (accpltm<5:0>) rf sequencer reset 1-255 clocks (rsttm<7:0>) 1-63 clocks (agcfsttm<5:0>) agc fast a+b-(c+d) bp1 ( ) 2 pd bp2 vco delay hysteresis comparator loop filter t- f f d-ff wobble clock wobble data xor
at78c1503 16 offset cancellation block the offset cancellation block allows the part to automatically cycle through many points in the part and remove electronic offsets which may be present. these electronic offsets in the signal path would cause larger signal distortion to be present, than if they are removed. several charge pump currents are also calibrated, which again, allows for very small dc offsets to be present on the integrating capacitors. the center frequencies of the two plls are also trimmed to optimized the given range that their filters operate over. finally, on-chip resistors are calibrated to remove any process variations. all calibration points can be seen in table 2 which describes each individual calibration point. all resulting offset calibration values may be read out by the user similar to any other serial register read operation. likewise, the user may program any of these offset values manually in the serial register just like any other memory location. any one or all of the calibration points can be cancelled per calibrator pass. the calstrt<5:0> bits determine which calibration point the calibrator will begin at and likewise the calend<5:0> bits determine where the calibrator will end. therefore, by programming the calstrt and calend bits to different values any or all of the points may be calibrated. the calibration sequence starts when the calbgn, calibration begin, bit is programmed from low to high. it is necessary to reprogram calbgn low, in order to prepare for a second calibration cycle. once the transition of calbgn is detected the calibrator begins to cycle through the chosen points. as the calibrator is running, serial register access to memory locations 97 through 115 must be avoided as the calibrator takes control of theses serial register locations while running. the adcen bit must always be programmed low when calibrating as this puts the calibrator into adc mode. the calibrator normally runs off from a fref divided by 4 clock and requires 50 clock cycles per calibration point. the user can determine the amount of system time required for a full calibration given the fref frequency and the number of calibration points. in every calibration offset register space the lsb is named calclk. when this bit is programmed low, the calibrator system clock is as described above. if this bit is programmed low for a particu- lar calibration point, then that calibration point will have a reduced system clock rate given by table 32. this allows different system clocks to be used for different calibration points as several of the points need to be ran slower, such as the pll center frequency. all calibration points have default values chosen for related gains and dacs. if a value other than the default is required, the calusesr, calsrvusesr and calpllusesr bits can be programmed high to use values from the serial register. the calusesr forces all agc related calibration points to use the pgc setting from the serial register. the calusesr also forces the lpf cutoff frequency to be determined from the serial register. the calsrvusesr bit forces the slow servo related calibration points to have their gains originate from the serial register and finally the calpllusesr forces the plls to have their settings come from the serial register. normally all three of these bits should be programmed low and the default values used. for test purposes, all internal calibration signals may be brought out of the cmos test points, data<7:0>. adc block the adc analog to digital converter block allows the part to digitized many of its own analog signals. the adc uses the calibrators ? 7-bit sar (successive approximation register), algorithm to digitize the output points shown in table 34. the adc can be used both for testing the part and possible self diagnostics when in a larger system. in order to put the calibrator into the adc mode the adcen bit needs to be programmed high. to begin an adc cycle, the adcstrt pin is then toggled from low to high. this pin may be returned low after 1 s even though the adc cycle may not be complete. the adc will then dig- itize the selected point and write the final value back into memory location 119. the final adc value may also be brought directly out on the data<6:0> lines by program- ming the adcouten bit high. data<7> will toggle after the final value is stable on the data<6:0> lines and may therefore be used as a clock line to latch in the adc value. the adc will only convert one point per adcstrt pulse unlike the calibrator which cycles through many points. four different input ranges are selectable at the input of the adc. this allows signals of different amplitudes to use the full range of the adc. the adcgain<1:0> bits control this range setting according to table 35. the translation of final digital value of the adc thus depends on the range setting. the digital value is a sign magnitude representation thus the msb represents the sign while the 6 lsb have a full scale reading dependent upon adcgain. the adcintshrt bit allows the adc to store any elec- tronic offset all the way from the signal source. it forces the same short circuitry to be used as when the part is being calibrated when programmed high. with adcintshrt is programmed low, the adc removes any offset which is present from the pin to the input of the adc comparator and thus gives the actual value present on the pin. it should also be noted that with adcsel set to 7, the trsin1p
at78c1503 17 input is selected which allows for any external signal to be converted. in conjunction with the adc function which digitizes various outputs, the part also has the capability to force dc offset voltages at all the signal inputs. this is very useful for dc tests in which many of the internal gains gain can be verified with no external hardware. a dc value can be forced at the input and the resulting output at any of the test points can be digitized by the adc and read out the serial register interface. the forcevin, force voltage input, bit enables current sources and switches the input ac coupling blocks to generate zero tc voltages. while this bit is programmed high, no attempt should be made to use the part with actual data. the forcesel<2:0> bits determine which input will have the offset voltage on it, see table 36. the amount of offset is determined by forceval<2:0> bits, see table 37. since the rf path and the slow servo path internally use different input stages, their respective offset voltages are different as shown with the two separate columns in table 37. figure 15. serial port timing diagram sena sclk rnw a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 sdata tec tpw
at78c1503 18 *disclaimer to users of this table. the location of some (if not all) of the bits in this serial register will probably change. write your code in order to minimize the impact of such changes, e.g., define these bit locations in only one place in your program. table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted. 0 7 agccaltpon enable cal test point selection, disable tp1<5:0> from controlling the outputs on tp1 respectively 6 tp1en test point 1 enable 5:0 tp1ser<5:0> test point 1 (agc) selection; see table 6 1 7unused 6 tp2en test point 2 enable 5:0 tp2ser<5:0> test point 2 (lpf) selection; see table 8 2 7 detshrtr short a 60k resistor across the detector charge pump output 6 tsdden test point tsdd1 & tsdd2 enable 5:0 tsdd1ser<5:0> test point tsdd1 (dcr, dpd, tr) selection; see table 18 3 7unused 6 tpshrtser short all test points 5:0 tsdd2ser<5:0> test point tsdd2 (dpd, tr, synth) selection; see table 23 4 7 accpl_slow 6:0 anseser<6:0> analog single ended selection; see table 24 5 7 sleepser sleep bit, get or ? d with the porb pin to power down entire part 6:1 unused<5:0> 0 pgcen programmable gain mode enable for the agc 6 7:4 agcqp<3:0> agc loop charge pump currents; see table 4 3 fltrbyp bypass low-pass filter inside the agc loop 2 agchbw enable agc high band width mode during fast recovery 1 sqlchser squelch 0unused 7 7:4 pgc<3:0> programmable gain magnitude for front-end vgas; see table 5 3:2 vgamode<1:0> input range select for front-end vgas; see table 3 1 rf_acbyp bypass ac-coupling capacitors 0 8p5x_acbyp bypass ac-coupling capacitors for the high-gain amplifier
at78c1503 19 8 7:5 bst1<3:0> rf lpf zero 1 location see table 30 4:2 bst2<3:0> rf lpf zero 2 location, see table 30 1 asymbst rf lpf asymmetric boost; if asserted, the zeros in the lpf are adjusted independently thus allowing adjustable group delay, if not asserted bst1<3:0> controls the symmetric zeros 0fltrgain rf lpf gain. allows the signal through the lpf to be halved; this is necessary for boost settings over 7 db 9 7:5 fltrrange<2:0> rf lpf range. sets the course lpf cutoff; see table 29 4:0 fcdac<4:0> rf lpf cutoff. sets the fine lpf cutoff within the range specified by fltrrange<2:0> 10 7:6 detkcpi<1:0> detector charge pump current; see table 10 5:4 detkcp<1:0> detector charge pump current multiplier; see table 10 3 detrst reset the detector loop filter 2 detqpup detector charge pump, pump-up in test mode 1 detqpdn detector charge pump, pump-down in test mode 0unused 11 7:5 detqpofrng<2:0> detector charge pump offset dac gain 4:2 detthrrng<2:0> slicer threshold range in open-loop mode 1:0 detmode<1:0> detector mode selection; see table 9 12 7unused 6:0 detthrsh<6:0> slicer threshold in open-loop mode 13 7unused 6 calplluseser calibrator use serial register location for plls 5:0 calstrt<5:0> calibrator start point, allows the calibrator to begin at any point according to table 2 14 7 calusesrser calibrator use serial register values 6 calsrvusesrser calibrator use serial register values for servo 5:0 calend<5:0> calibrator end point; allows the calibrator to end at any point according totable 2 15 7 calbgn calibration begin; toggling this bit from low to high starts a calibration cycle 6:5 calclk<1:0> calibration clock setting; determines the calibrator system clock if calclk bit is high for the particular calibration address; if calclk bit is low then calibrator system clock equals fref divided by four; seetable 32 4:0 rfdth<4:0> rd dropout threshold; set the minimum signal level that the rf signal need to drop below to qualify as a dropout table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 20 16 7 rdszen enable read size buffer 6 rdszsel select read size buffer output (1 = agc cap voltage, 0 = detector loop filter voltage) 5 rfdropen rf dropout enable. enables the rf dropout to operate 4:0 rfdropcnt<4:0> rf dropout count. duration that the dropout detector looks for lack of signal before asserting the rfdrop relative to the synthesizer divided by 2 cycles 17 7:0 acq_cnt<7:0> acquisition count. following the rising edge of rg, acquisition mode lasts (acquisition count +1) 4 tr vco cycles 18 7:3 drdac<4:0 sets vco center frequency. also sets pll filter components and charge pump currents for automatically selected mode. see table 17 2:1 trsymf<1:0> manual tr and synthesizer pll filter and qp current selector. see table 12 0 nibble parallel data out 4 bits wide when high, 8 bits wide otherwise 19 7:4 acq_flt<7:4> manual tr pll filter r acquisition mode setting. see table 12, table 13 3:0 acq_flt<3:0> man tr pll filter cs acquisition mode setting. see table 12, table 16 20 7:4 trk_flt<7:4> manual tr pll filter r tracking mode setting. see table 12, table 13 3:0 trk_flt<4:0> manual tr pll filter cs tracking mode setting. see table 12, table 16 21 7:4 trk_cpi<3:0> manual tr tracking charge pump current, see table 11, table 12 3:0 acq_cpi<3:0> manual tr acquisition charge pump current, see table 11, table 12 22 7 pd_fe tr phase detector active on data falling edge only 6 pd_re tr phase detector active on data rising edge only 5 nrz recovered data in nrz format (nrz high) recovered data 1 on transition, 0 otherwise (dvd format) (nrz low) 4 r_dat reset data flip-flops in detector 3 trs_pd set pd flip-flop in tr phase-frequency detector 2 trs_pu set pu flip-flop in tr phase-frequency detector 1 trr_pupd reset pu and pd flip-flops in tr phase-frequency detector 0 trr_div4 reset divide by 4 flip-flops in tr phase-frequency detector 23 7 tr_hdt gives tr high damping ratio (1.6) during tracking mode 6 watchcal tr and synthesizer calibration error signal appears on test point 5 extrv external clock replaces tr vco 4 exdata external data muxed into tr detector 3:2 rst_mnp<1:0> reset synthesizer ? s m, n and p counters 1 sleep_sy independently sleeps synthesizer 0 sleep_tr independently sleeps tr 24 7:4 syn_flt<7:4> manual synthesizer pll filter r setting. see table 12, table 13 3:0 syn_flt<3:0> manual synthesizer pll filter cs setting. see table 12, table 16 table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 21 25 7 shortcst short tr ? s pll filter cap, cs 6 shortcss short synthesizer ? s pll filter cap, cs 5unused 4 syhidmp synthesizer pll filter hi damping; increase default r by 50% 3:0 syn_cpi<3:0> manual synthesizer charge pump current, see table 11, table 12 26 7unused 6 frefby2 divide the frequency reference input on the fref pin by 2 5 exsyv external synthesizer vco substituted for regular synthesizer vco 4 exsyck external reference clock mux ? d into synthesizer detector 3 sys_pd set pd flip-flop in synthesizer phase-frequency detector 2 sys_pu set pu flip-flop in synthesizer phase-frequency detector 1 syr_pupd reset pu and pd ff ? s in synthesizer phase-frequency detector 0 syr_div4 reset divide by 4 ff ? s in synthesizer phase-frequency detector 27 7 p<2> synthesizer p count msb 6:0 m<6:0> synthesizer m count 28 7:6 p<1:0> synthesizer p count two lsbs 5:0 n<5:0> synthesizer n count 29 7:3 unused 2:0 selextrm<2:0> trim bandgap voltage to 1.2 volts 30 7:4 3:0 bqd1q<3:0> adjusts biquad1 ? s q in the rf lpf; see table xxx 31 7:4 bqd3q<3:0> adjusts biquad2 ? s q in the rf lpf; see table xxx 3:0 bqd2q<3:0> adjusts biquad3 ? s q in the rf lpf; see table xxx 32 7 blkwbl holds wobble output low when in ram header 6 idinitser allows an internally detected header to start sequencer 5 rgstrt rg start. allows the rising edge of rg to start sequencer 4:1 agclztm<3:0> synthesizer nibble count for sequencer lowz time 0 snglhdr puts sequencer in single header mode, if hdratmg is asserted, only one header sequence is timed out 33 7:2 accpltm<5:0> synthesizer nibble count for sequencer fast recovery time 1datrefst timing recovery data reference start, when high, the or ? ing of rg and idsel go straight to timing recovery pll 0 hdratmg header auto-timing, when high the sequencer controls the agc and tr pll control lines table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 22 34 7:2 agcfsttm<5:0> synthesizer nibble count for sequencer tr reference time 1 sidtstinput 0 dissqcr disable sequencer 35 7:0 rsttm<7:0> synthesizer nibble count for sequencer reset time; useful to automatically turning off headers, this has no effect when reading user data 36 7:4 idwblvga<3:0> id/wobble vga gain, set id/wobble gain according to table xx 3 idwblacbyp id/wobble ac coupling bypass, this is used for testing in order to get dc signal to the id and wobble filters 2 idhld id hold, when high id12 and id34 outputs can only change when idsel is asserted 1 hdrtsten header test enable, allows testing of the id detector state machine 0polpol polarity of the polarity, allows the polarity of the land/groove transition to be programmed. when low, if first header is positive, the polarity of the tracking error is positive, when high, the tracking error is inverted 37 7:4 idslce<3:0> id slice level, determines the level that is necessary to qualify a valid header, see table xxx 3:2 wbl<1:0> wobble slice level, determines the level that is necessary to qualify the wobble signal following the bpf, see table xxx, this level is dependent on the wblen bit 1 wblen wobble level enable, when low, the wobble slicer compares around zero, when high the slicer input depends on wbl<1:0> 0 ramread ram read, forces the tr pll to switch to phase/frequency mode during the header preambles 38 7:5 idwblfltr<2:0> id/woble filter, controls the id filters lpf cutoff and the wobble filter bandpass center frequency 4 idfldsrce id field source, determines whether the idfield will follow idsel pin or the internally generated id header signal 3 ansesi2pin 2:0 unused 39 7 rfgen generate the rf signal internally using fo1, fo2, tr1 & tr2 6:3 srvmod<3:0> 2 sendeddvdser 1 prmpinvdvdser 0 prmpinvcdser table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 23 40 7 cmostp03en cmos test points 0-3 enable; when asserted, nrz<3:0> function as cmos test outputs according to table 25 6 cmostp47en cmos test points 4-7 enable; when asserted, nrz<4:7> function as cmos test outputs according to table 25 5:1 cmostp<4:0> cmos test point selection; choose which digital signals to output on nrz<7:0> pins dependent on cmostp03en and cmostp47en 0 ansetpon 41 7:4 trmvrefin<3:0> 3:0 trmvrefoutn<3:0> 42 7sintrefin 6sintrefout 5 enansein 4 entstsum 3:0 tstsum<3:0> 43 7tstmod 6tstld 5tstud 4tstrstser 3 avglpfsel 2 dis_lbw_ss 1bwupser 0 bwdwnser 44 7:4 strtdivhi<3:0> 3:0 stopdivlo<3:0> 45 7:4 acmcntmir<3:0> 3:0 acmcnttzc<3:0> 46 7:4 avghystmir<3:0> 3:0 avghysttzc<3:0> 47 7:2 agctzcser<5:0> 1 sagctzcser 0lowgavgtzc 48 7:2 agcmirser<5:0> 1sagcmirser 0lowgavgmir table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 24 49 7:4 gsel<3:0> 3:0 bwsel<3:0> 50 7:4 gsel_cdtr<3:0> 3:0 bwsel_cdtr<3:0> 51 7:3 fo1kgadjn<4:0> 2:0 rtrmfe<2:0> 52 7:3 fo1kofadj<4:0> 2foi2vhig 1 sgnfeoff 0unused 53 7:3 fo2kgadjn<4:0> 2:0 feoff<2:0> 54 7:3 fo3kofadj<4:0> 2:0 shinpsel<2:0> 55 7:3 tr1kgadjn<4:0> 2:0 rtrmte<2:0> 56 7:3 tr1kofadj<4:0> 2tri2vhig 1 sgnteoff 0 selte 57 7:3 tr2kgadjn<4:0> 2:0 teoff<2:0> 58 7:3 tr2kofadj<4:0> 2:0 unused 59 7:3 tr1cdkgadjn<4:0> 2:0 unused 60 7:3 tr1cdkofadj<4:0> 2:0 unused 61 7:3 tr2cdkgadjn<4:0> 2 selramsum_zc 1:0 unused 62 7:3 tr2cdkofadj<4:0> 2 nrm_hirange 1:0 winnrm<1:0> table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 25 63 7:2 trmnrm<5:0> 1:0 kthnrm<1:0> 64 7 selhbsfo12 6 selhbstr12 5 nrlowg 4:3 nrctmod<1:0> 2srvwrenb 1 srvholddis 0 srvlddsb 65 7:3 srvdivclk<4:0> 2 srvselclk 1 ennrmhold 0mrfldv84 66 7:3 gsel_lensp<4:0> 2 enlensp 1 polensp 0en_idfhold 67 7:4 fegi2vhig<3:0> 3:0 fegi2vhog<3:0> 68 7:4 tegi2vhig<3:0> 3:0 tegi2vhog<3:0> 69 7:4 fegout<3:0> 3:0 tegout<3:0> 70 7:4 ssgi2v<3:0> 3:0 ssgout<3:0> 71 7:4 ghbsumn<3:0> 3:0 kthmir<3:0> 72 7:4 kthfokrd<3:0> 3:0 kthfokwr<3:0> 73 7:4 kthtokrd<3:0> 3:0 kthtokwr<3:0> 74 7 nrwrdtr 6:1 nrdatar<6:0> 0 dflt71<0> table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 26 75 7 nrwrdtr 6:1 nrdatar<6:0> 0 dflt71<0> 76 7 dpdvgabyp bypass front-end vgas inside the dpd 6:5 dpdvgamode<1:0> mode selection for front-end vgas inside the dpd 4:1 dpdkpgc<3:0> gain selection for front-end vgas inside the dpd 0unused 77 7 dpdlpfbyp bypass 1st order low-pass filter inside the equalizer 6:4 dpdfc<2:0> dvd setting (1 through 5) 3 dpdqpsqlch squelch dpd charge pump output 2 dpdenrmres enable loop filter resistor removal during dpd hold 1 dpdrmres remove loop filter resistor 0unused 78 7:5 dpdqprng<2:0> dpd charge pump offset dac gain 4:3 dpdcpi<1:0> dpd charge pump current; see table 10 2:1 dpdkcp<1:0> dpd charge pump current multiplier; see table 10 0 dpdpdrst reset phase detector inside the dpd 79 7 dpdaclead test signal; diagonal (a+c) leads diagonal (b+d) 6 dpddisact test signal; disable (a+c) input to the phase detector 5 dpddisbdt test signal; disable (b+d) input to the phase detector 4 dpddishld disable missing pulse detector 3:0 dpdksevga<3:0> single-ended vga gain selection; see table 21 80 7:4 dpdfcdac<3:0> 20% adjust on equalizer pole/zero frequency; see table 22; 3 dpddivsel low-pass filter bandwidth divide-by factor 2:0 unused 81 7:4 dpddivhi<3:0> bandwidth divider (high value) 3:0 dpddivlo<3:0> bandwidth divider (low value) 82 7 adcen adc enable. switches the calibrator from calibration mode to adc mode when programmed high 6:5 adcgain<1:0> adc gain. determines the maximum adc input, see table 35 4 adcouten adc output enable. allows the adc final value to be strobes out on nrz<7:0> pins 3 adcintshrt adc internal short. when this pin is high, the internal short circuitry normally used during offset calibration is also used by the adc. 2 adcselser<2:0> adc input selection. determines which pin will be converted by the adc, see table 34 table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 27 83 7:0 unused calibration serial register locations 96 7:0 unused 97 7:3 vga0off<4:0> 2:1 unused 0calclk 98 7:3 vga1off<4:0> 2:1 unused 0calclk 99 7:3 vga2off<4:0> 2:1 unused 0calclk 100 7:3 vga3off<4:0> 2:1 unused 0calclk 101 7:3 vga4off<4:0> 2:1 unused 0calclk 102 7:2 a10off<5:0> 1unused 0calclk 103 7:6 resoff<1:0> 5:1 unused 0calclk 104 7:1 fltinoff<6:0> 0calclk 105 7:1 bqd2off<6:0> 0calclk 106 7:1 dcroff<6:0> 0calclk 107 7:3 dpdvga1off<4:0> 2:1 unused table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 28 0calclk 108 7:3 dpdvga2off<4:0> 2:1 unused 0calclk 109 7:1 dpdqpoff<6:0> 0calclk 110 7:1 syqpoff<6:0> 0calclk 111 7:1 trqpoff<6:0> 0calclk 112 7:3 syicotrm<4:0> 2:1 unused 1calclk 113 7:3 tricotrm<4:0> 2:1 unused 1calclk 114 7:1 trmfe<6:0> 0calclk 115 7:1 trmte<6:0> 0calclk 116 7:0 unused 117 7:0 unused 118 7:0 unused 119 7:0 unused table 2. serial register calibration address space serial register address cal decode <5:0> number of bit(s) description (** dacs must be sign magnitude **) 96 0 test na 97 1 4:0 vga0 internal node 98 2 4:0 vga1 99 3 4:0 vga2 100 4 4:0 vga3 101 5 4:0 vga4 102 6 5:0 amp10 output table 1. serial register bit map reg bit(s) name description ** all bits active-high unless otherwise noted. ** all dacs linear unless otherwise noted.
at78c1503 29 103 7 1:0 resistor dac 104 8 5:0 filter input 105 9 5:0 filter midpoint (bqd2 output) 106 10 5:0 dcr charge pump offset 107 11 5:0 dpd vga (a+c) 108 12 5:0 dpd vga (b+d) 109 13 5:0 dpd charge pump offset 110 14 6:0 synthesizer charge pump offset 111 15 6:0 tr charge pump offset 112 16 4:0 synthtr vco center frequency 113 17 4:0 tr vco center frequency 114 18 115 19 116 20 117 21 118 22 119 23 table 2. serial register calibration address space serial register address cal decode <5:0> number of bit(s) description (** dacs must be sign magnitude **)
at78c1503 30 table 3. rf input range selection vgamode <1:0> operating mode 00 110-1100 mv 01 60-600 mv 10 30-300 mv 11 30-300 mv table 4. charge pump current selection (charging current) agcqp <3:0> charging current (a) 0000 11.25 0001 13.125 0010 15.00 0011 16.875 0100 18.75 0101 20.625 0110 22.50 0111 24.375 1000 26.25 1001 28.125 1010 30.00 1011 31.875 1100 33.75 1101 35.625 1110 37.50 1111 39.375 table 5. pgc mode gain settings pgc <3:0> vga voltage gain low moderate high 0000 0.06 0.121 0.474 0001 0.067 0.134 0.528 0010 0.075 0.150 0.592 0011 0.084 0.169 0.667 0100 0.096 0.191 0.759 0101 0.109 0.219 0.870 0110 0.126 0.253 1.008 0111 0.148 0.296 1.181 1000 0.176 0.352 1.404 1001 0.212 0.424 1.694 1010 0.261 0.523 2.085 1011 0.330 0.660 2.627 1100 0.429 0.858 3.408 1101 0.581 1.162 4.590 1110 0.830 1.660 6.505 1111 1.280 2.558 9.917 table 6. tp 1 selection address non calibration mode and (agccaltpon = 0) tp1 <5:0> test signal 000000 vga0 input 000001 vga0 output 000010 vga1 input 000011 vga1 output 000100 vga2 input 000101 vga2 output 000110 vga3 input 000111 vga3 output 001000 vga4 input 001001 vga4 output 001010 dtr1 (differential tracking 1) 001011 dtr2 (differential tracking 2) 001100 ac couple input 001101 amp10 input 001110 amp10 output 001111 na table 7. test point 1 calibration selection address (agccaltpon = 1) tp1 <5:0> gain 000000 na 000001 vga0 internal node 000010 vga1 internal node 000011 vga2 internal node table 5. pgc mode gain settings pgc <3:0> vga voltage gain low moderate high
at78c1503 31 000100 vga3 internal node 000101 vga4 internal node 000110 amp10 output table 8. test point 2 mapping tp2 <5:0> test point 2 signal 32 filter input (from vga) 33 filter input (re-referenced) 34 bqd1 internal 35 bqd1 output (unbuffered) 36 bqd2 input (bqd1 output buffered) 37 bqd2 internal 38 bqd2 output, lp input 39 lp output, bqd3 input 40 bqd3 internal 41 bqd3 output (unbuffered) 42 bqd3 output (buffered) table 9. detector modes of operation detmode <1:0> operating mode 00 dc restore mode 01 write power test mode 10 don ? t use 11 comparator mode table 10. detector charge pump currents detcpi<1:0>, detkcp<1:0> current (a) 0000 4.86 0001 5.69 0010 6.80 0011 8.46 0100 9.20 0101 10.76 0110 12.88 0111 16.01 table 7. test point 1 calibration selection address (agccaltpon = 1) tp1 <5:0> gain 1000 19.32 1001 22.60 1010 27.05 1011 33.62 1100 38.40 1101 44.93 1110 53.76 1111 66.82 table 11. manual charge pump currents vs. qpi dac setting qpi dac current (a) 0000 4.86 0001 5.69 0010 6.80 0011 8.46 0100 9.20 0101 10.76 0110 12.88 0111 16.01 1000 19.32 1001 22.60 1010 27.05 1011 33.62 1100 38.40 1101 44.93 1110 53.76 1111 66.82 table 12. manual pll filter and qp current selection trsymf selection 00 all automatic 01 only synthesizer r & qpi manual 10 only synthesizer r, c & qpi manual 11 tr & synthesizer all manual table 10. detector charge pump currents detcpi<1:0>, detkcp<1:0> current (a)
at78c1503 32 table 13. manual pll filter r settings trsymf (binary) r (k ? ) 0000 0.5 xxx1 add 17.8 xx1x add 26.8 x1xx add 18.3 1xxx add 22.3 table 14. tssd test point 1 mapping tsdd1 <3:0> tr, synthesizer, dc restore, dpd test point 1 0 dc restore slicer input 1 dc restore capacitor voltage 2 dpd vga input (a+c) 3 dpd vga output (a+c) 4 dpd lp filter output (a+c) 5 dpd equalizer output (a+c) 6 dpd comparator output (a+c) 7 8 tr pump up 9 synthesizer pump up 10 tr raw data (input data from dc restore block) 11 recovered clock (recovered from raw data stream) 12 (fltb) tr loop filter, buffered 13 (fcsb) tr loop filter large cap, buffered 14 (fltu) tr loop filter, unbuffered 15 (fcsu) tr loop filter large cap, unbuffered table 15. tsdd test point 2 mapping tsdd2 <3:0> tr, synthesizer, dc restore, dpd test point 2 0 dpd vga input (b+d) 1 dpd vga output (b+d) 2 dpd lp filter output (b+d) 3 dpd equalizer output (b+d) 4 dpd comparator output (b+d) 5 synthesizer n, differential signal 6 synthesizer m, differential signal 7 synthesizer vco/4, differential signal 8 tr pump down 9 synthesizer pump down 10 tr recovered data (serial stream) 11 synthesizer vco 12 (fltb) synthesizer loop filter, buffered 13 (fcsb) synthesizer loop filter large cap, buffered 14 (fltu) synthesizer loop filter, unbuffered 15 (fcsb) synthesizer loop filter large cap, unbuffered table 16. manual pll filter cs settings (note: cp = cs/20) cs dac (binary) cs dac (decimal) cs (pf) 0000 0 0 0001 1 0 0010 2 54.5 0011 3 44.5 0100 4 36.4 0101 5 29.8 0110 6 24.5 0111 7 20.0 1000 8 16.5 1001 9 13.5 1010 10 11.0 1011 11 9.0 1100 12 9.0 1101 13 9.0 1110 14 9.0 1111 15 9.0 table 15. tsdd test point 2 mapping tsdd2 <3:0> tr, synthesizer, dc restore, dpd test point 2
at78c1503 33 table 17. tr and synthesizer automatic loop filter and charge pump settings data rate dac vco fc (mhz) r (k ? )charge pump ( a) cs (pf) f n (khz) z 3 or less off 42.8 20 0 na na 4 24.7 42.8 20 54.5 144 1.05 5 27.3 42.8 20 54.5 151 1.11 6 30.2 42.8 20 44.5 176 1.05 7 33.4 42.8 20 44.5 185 1.11 8 37.0 42.8 20 36.4 215 1.05 9 40.9 42.8 20 36.4 226 1.11 10 45.2 42.8 20 29.8 263 1.05 11 50.0 42.8 20 29.8 277 1.11 12 54.9 42.8 20 24.5 320 1.05 13 60.7 42.8 20 24.5 336 1.11 14 67.0 42.8 20 20.0 391 1.05 15 74.1 42.8 20 20.0 411 1.11 16 81.8 42.8 20 16.5 475 1.05 17 90.3 42.8 20 16.5 500 1.11 18 99.8 42.8 20 13.5 581 1.05 19 110.1 42.8 20 13.5 611 1.11 20 122.8 42.8 20 11.0 711 1.05 21 134.8 42.8 20 11.0 748 1.11 22 148.8 42.8 20 9.0 869 1.05 23 163.9 42.8 20 9.0 913 1.11 table 18. input/servo modes input mode12345 description of operation mode custom ring focus mode dvd rom with ring focus standard dvd rom standard dvd ram a,b,c,d mode fo1p/n a+b+c+d a+b+c+d a+c a+c a fo2p/n e+f+g+h e+f+g+h b+d b+d b tr1p/n a+b+e+f a+c+e+g a+c a+b c tr2p/n c+d+g+h b+d+f+h b+d c+d d
at78c1503 34 table 19. track zero cross tzc bandwidth comparator hysteresis 128 k 100 mv 256k 70 mv 512k 50 mv 1m 35 mv table 20. dpd equalizer pole/zero frequencies dpdfc<3:0> frequency (mhz) zero pole1 pole2 000 1 3.4 10 001 2 6.8 20 010 3 10.2 30 011 4 13.6 40 1xx 5 17 50 table 21. dpd single-ended vga gain dpdksevga <2:0> voltage gain (v/v) dpdksevga<3> = 0 dpdksevga<3> = 1 000 0.25 0.5 001 0.5 1.0 010 0.75 1.5 011 1.0 2.0 100 1.25 2.5 101 1.5 3.0 110 1.75 3.5 111 2.0 4.0 table 22. dpd equalizer cutoff frequency adjust dpdfcdac<3:0> cutoff frequency 0000 fc 0001 +3.12% 0010 +6.24% 0011 +9.36% 0100 +12.48% 0101 +15.6% 0110 +18.72% 0111 +21.84% 1000 fc 1001 -3.12% 1010 -6.24% 1011 -9.36% 1100 -12.48% 1101 -15.6% 1110 -18.72% 1111 -21.84% table 23. dpd low-pass filter cutoff frequency (dpddivsel = 1) dpddivhi<3:0> frequency (khz) 0000 2500 0001 1300 0010 660 0011 340 0100 180 0101 100 0110 60 0111 40 1xxx 30 table 24. analog single-ended test point anse tp<5:0> analog single ended test point 0 avghysttzcp 1 avghysttzcn 2 avghystmirp 3 avghyst,irn 4 5 6 7 8 9 10 11 idwbl vga output 12 idwbl filter input table 22. dpd equalizer cutoff frequency adjust
at78c1503 35 13 id lpf output 14 wobble bpf output 15 id level p 16 id level n 17 wobble level 18 dpd se vga output 19 20 21 22 23 24 25 26 27 28 29 30 31 dacs from here down 32 vga1 pgc dac 33 vga2 agc qpump dac 34 fcdac 35 dc restore 1 36 dc restore 2 37 tr ico bias 38 sy ico bias 39 dpd vga pgc dac 40 dpd qp dac 41 rf drop dac 42 tr qp offset dac 43 sy qp offset dac 44 dpd gm hi 45 dpd gm lo 46 47 48 table 24. analog single-ended test point anse tp<5:0> analog single ended test point 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 table 24. analog single-ended test point anse tp<5:0> analog single ended test point
at78c1503 36 table 25. digital cmos test points cmos tp<4:0> data7 data6 data5 data4 data3 data2 data1 data0 0 calon caluesr shortcal ltch wstrobe comp update clkbit 1 calibration addr<5:0> incaddr cntdone 2 msbset calibration offsetout<7:1> 3 synthesizer m counter <7:0> 4 synthesizer n counter <7:0> 5 acqntrk pupdclr synthesizer p counter <2:0> 6 tr acquisition mode counter <7:0> 7dpd 8dpd 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 table 26. tr and synthesizer test input 1 mapping tr and synthesizer test input 1 replace tr vco if serial register bit extrv is true replace synthesizer vco if serial register bit exsyv is true table 27. tr and synthesizer test input 2 mapping tr and synthesizer test input 2 replace raw data input to tr if serial register bit exdata is true replace synthesizer vco if serial register bit exsyck is true table 28. servo mode tr and synthesizer test input 2
at78c1503 37 table 29. filter range fltrrange<2:0> lpf cutoff (mhz) 0 2.6 - 3.8 1 3.9 - 5.8 2 5.8 - 8.7 3 7.8 - 11.8 4 11.58 - 17.3 5 17.4 - 26 table 30. lpf boost settings bst<2:0> (asymbst=0) maximum boost above unboosted -3db point (db) 00 1+1 2+3 3+5.8 4+9 5+12 6+15 7+17 table 31. filter biquad q adjustment bqd1-3<3:0> table 32. calibrator system clock calclk<1:0> fref divide by 032 164 2 256 3 512 table 33. wobble comparator level wbllvl<1:0> level 0 0 +52 mv 0 1 +104 mv 1 0 -52 mv 1 1 -104 mv table 34. adc input selection adcval<2:0> adc signal adc reference 0 anse as required by signal 1 tp1 0v differential 2 tp2 0v differential 3 tsdd1 0v differential 4 tsdd2 0v differential 5 vbg refback 6 rdsz refback 7 trsin1p refback table 35. adc maximum signal range settings adcgain<1:0> maximum adc input signal (vdiffpp) 0 0.125 1 0.25 20.5 31.0 table 36. input voltage offset selection forcesel<2:0> selected input 0fo1 1fo2 2tr1 3tr2 4cdfo1 5cdfo2 6 cdtr1 7 cdtr2
at78c1503 38 electrical specifications operating conditions: v dd = 3.0 - 3.6 volts and t a = 0 - 70 c table 37. forced input voltage amplitude forceval<2:0> rf offset (mv) servo offset (mv) 05055 1 100 170 2 200 280 3 400 400 4-50-55 5 -100 -170 6 -200 -280 7 -400 -400 table 37. forced input voltage amplitude forceval<2:0> rf offset (mv) servo offset (mv) supply specifications parameter sym conditions min typ max units supply voltage vdd 3.0 3.3 3.6 v supply current idd 275 ma sleep mode current idds 100 a digital input/output (cmos compatible) parameter sym conditions min typ max units high-level input voltage v ih v dd -0.5 v low-level input voltage v il 0.5 v high/low level input current 10 ma high-level output voltage v oh i oh = 0.5 ma v dd -0.2 v low-level output voltage v ol i ol = 0.5 ma 0.4 bandgap reference parameter sym conditions min typ max units output voltage vbg 1.15 1.2 1.25 v reference resistor rext reference resistor from vbg to vss (ground) 16.2 k ?
at78c1503 39 variable gain amplifier (vga) parameter sym conditions min typ max units gain range 110v/v input dynamic range (low-mode) drl 30 300 mv input dynamic range (high-mode) drh 60 600 mv bandwidth agcbw -3db 100 mhz agc control sensitivity agc mode 20 db/v agc locking voltage (input to data slicer) vagc peak-to-peak differential input to slicer in agc mode 1v total harmonic distortion thd measured at the detector input. 750 mvppd lock in agc mode 2% common mode rejection ratio cmrr vin = 250 mv common mode @10 mhz 40 db power supply rejection ratio psrr vsup = 250 mv @10 mhz 40 db 7th order equiripple filter/equalizer parameter sym conditions min typ max units filter cutoff frequency programmability fc 4.4 22 mhz filter boost range fb measured from low frequency gain 013db cutoff frequency accuracy all frequency ranges -10 +10 % boost accuracy all frequency ranges -2 +2 db group delay variation all frequency ranges -4 +4 % data phase locked loop parameter sym conditions min typ max units frequency supported 26 146 mhz rms jitter tbd degrees pull-in range -2.5 +2.5 % of fc frequency synthesizer parameter sym conditions min typ max units frequency supported 26 146 mhz external source 15 40 mhz
at78c1503 40 serial register parameter sym conditions min typ max units serial clock frequency sclk 0.01 20 mhz sena to sclk set-up time tec transition time serial enable to serial clock 10 ns sclk pulse width tpw 20 ns sclk to sdata hold time thcd 10 ns sdata to sclk set-up time tsdc 10 ns table 38. pin list pin # pin name type description 1 idfield output signal to preamp to drive id select 2 rfp analog input high-speed signal input 3 rfn analog input high-speed signal input 4 fo1p differential input focus 1 positive 5 fo1n differential input focus 1 negative 6 fo2p differential input focus 2 positive 7 fo2n differential input focus 2 negative 8 tr1p differential input track 1 positive 9 tr1n differential input track 1 negative 10 tr2p differential input track 2 positive 11 tr2n differential input track 2 negative 12 fohg 13 rext passive passive for 0 tc current reference 14 vdd1 +3.3v supply dpd, ibias 15 vss1 0 v supply dpd, ibias 16 fo1_cd analog input focus 1, cd input 17 fo2_cd analog input focus 2, cd input 18 tr1_cd analog input track 1, cd input 19 tr2_cd analog input track 2, cd input 20 vdd6 +3.3v supply slow servo analog 21 ss_h 22 vss6 0v supply slow servo analog 23 reffront input/output servo front-end reference level 24 refback input/output servo back-end reference level 25 lenspos analog input lens position error input
at78c1503 41 26 atp1 analog input servo analog test point 27 fe analog output focus error output 28 te analog output tracking error output 29 slowsum analog output low-pass filtered sum of photodetector outputs 30 porb 31 vss8 servo dacs 32 vdd8 servo dacs 33 idsel input id field select 34 lhipwr input laser high power 35 shld input servo hold 36 adcstrt digital input start on-chip 6-bit adc 37 bwup digital input bandwidth up 38 bwdn digital input bandwidth down 39 idint input mode select of sequencer 40 pd input power down 41 rg input user data read gate 42 vss9 servo dac rings 43 vdd9 servo dac rings 44 wobble digital output wobble detect output 45 id12 digital output id field 12 detected 46 id34 digital output id field 34 detected 47 tzc digital output track zero crossing 48 tok digital output track ok 49 fok digital output focus ok 50 mirror output mirror detect (rom)/mirror field detect (ram) 51 sena input serial data enable; must be high to read or write serial registers 52 sdata input/output serial data, input (write data) or output (read data) 53 sclk input serial data clock 54 vss4 esd ring, digital ring 55 vdd4 esd ring, digital ring 56 vss7 slow servo digital, synthesizer dividers 57 vdd7 slow servo digital, synthesizer dividers 58 fref digital input reference clock input to synthesizer 59 vss5 0v supply digital i/o supply 60 vdd5 3.3v supply digital i/o supply 61 rfdrop digital output rf dropout detected table 38. pin list pin # pin name type description
at78c1503 42 62 rclk digital output recovered clock divided by 4 or 8 63 data0 output recovered data out, bit 0 (last in time) 64 data1 output recovered data out, bit 1 65 data2 output recovered data out, bit 2 66 data3 output recovered data out, bit 3 67 data4 output recovered data out, bit 4 68 data5 output recovered data out, bit 5 69 data6 output recovered data out, bit 6 70 data7 output recovered data out, bit 7 (first in time) 71 vss11 0v supply digital i/o ring 72 vdd11 +3.3v supply digital i/o ring 73 vss3 0v supply tr cml, synthesizer cml, dc restore 74 vdd3 +3.3v supply tr cml, synthesizer cml, dc restore 75 trcst input timing recovery coast 76 wclk output write clock 77 wg input write gate (enables write clock) 78 trsin2n differential input timing recovery/synthesizer test input 79 trsin2p differential input timing recovery/synthesizer test input 80 trsin1n differential input timing recovery/synthesizer test input 81 trsin1p differential input timing recovery/synthesizer test input 82 tsddtp1n test output tr/detector/phase detector test point 83 tsddtp1p test output tr/detector/phase detector test point 84 tsddtp2n test output tr/detector/phase detector test point 85 tsddtp2p test output tr/detector/phase detector test point 86 cdcrn analog detector duty cycle feedback cap 87 cdcrp analog detector duty cycle feedback cap 88 vdd2 +3.3v supply rf frontend ring 89 vss2 0v supply rf frontend ring 90 tp2n differential output test point 2 output 91 tp2p differential output test point 2 output 92 tp1n differential output test point 1 output 93 tp1p differential output test point 1 output 94 agchld digital input agc hold input 95 agcfst digital input agc fast recovery input 96 vss10 agc, lpf 97 vdd10 agc, lpf table 38. pin list pin # pin name type description
at78c1503 43 98 agclz digital input low z control for agc input 99 rdsz analog output agc cap/detector cap voltage outputs 100 cagc passive external capacitor for agc loop table 38. pin list pin # pin name type description table 39. supply pins supply pin circuitry vdd/ss1 dpd, ibias, rtrim vdd/ss2 rf frontend ring vdd/ss3 tr & synthesizer cml, dc restore, rf dropout analog vdd/ss4 esd & digital ring vdd/ss5 digital i/o supply vdd/ss6 servo analog vdd/ss7 servo, synthesizer and rf dropout digital, cmostpmux, serial registers 1&3, calibrator vdd/ss8 servo dacs vdd/ss9 servo dac rings vdd/ss10 agc, lpf vdd/ss11 digital i/o ring
at78c1503 44 ordering information ordering code package operation range at78c1503-100tc 100 pin tqfp commercial (0 c to 70 c) AT78C1503-100LC 100 pin lqfp commercial (0 c to 70 c) package type 100t 100-lead, thin quad flat pack (tqfp) 100l 100-lead, low quad flat pack (lqfp)
at78c1503 45 packaging information pin 1 id 0.56(0.022) 0.44(0.018) 16.25(0.640) 15.75(0.620) 0.27(0.011) 0.17(0.007) 14.10(0.555) 13.90(0.547) 0.15(0.006) 0.05(0.002) 0.75(0.030) 0.45(0.018) 0-7 0.20(0.008) 0.10(0.004) 1.05(0.041) 0.95(0.037) 100t , 100-lead, thin quad flat pack (tqfp) dimensions in inches and (millimeters) 100l , 100-lead, low quad flat pack (lqfp) dimensions in millimeters pin 1 id 0.56 0.44 16.25 15.75 0.27 0.17 14.10 13.90 0.15 0.05 0.75 0.45 0-7 0.20 0.10 1.45 1.35
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